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HD74ACT161/HD74ACT163
Synchronous Presettable Binary Counter
REJ03D0279-0200Z (Previous ADE-205-402 (Z)) Rev.2.00 Jul.16.2004
Description
The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.
Features
* Synchronous Counting and Loading * High-Speed Synchronous Expansion * Typical Count Rate of 125 MHz * Outputs Source/Sink 24 mA * HD74ACT161 and HD74ACT163 have TTL-Compatible Inputs * Ordering Information: Ex. HD74ACT161
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-16DAV FP RP EL (2,000 pcs/reel) EL (2,500 pcs/reel)
HD74ACT161FPEL SOP-16 pin (JEITA)
HD74ACT161RPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code.
Pin Arrangement
*R 1 CP 2 P0 3 P1 4 P2 5 P3 6 CEP 7 GND 8 (Top view) 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 CET 9 PE
Rev.2.00, Jul.16.2004, page 1 of 8
HD74ACT161/HD74ACT163
Logic Symbol
PE P0 P1 P2 P3 CEP CET CP *R Q0 Q1 Q2 Q3 * MR for HD74ACT161 SR for HD74ACT163 TC
Pin Names
CEP CET CP MR (HD74ACT161) SR (HD74ACT163) P0 to P3 PE Q0 to Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output
Functional Description
The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-toHigh transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (HD74ACT161), synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs - Master Reste (MR, HD74ACT161), Synchronous Reset (SR, HD74ACT163), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) - determine the mode of operation, as shown in the Mode Select Table. A Low signal on MR overrides all other inputs and asynchronously forces all outputs Low. A Low signal on SR overrides counting and parallel loading and allows all outputs to go Low on the next rising edge of CP. A Low signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR (HD74ACT161) or SR (HD74ACT163) High, CEP and CET permit counting when both are High. Conversely, a Low signal on either CEP or CET inhibits counting. The HD74ACT161 and HD74ACT163 use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count (TC) output is High when CET is High and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations: Count Enable = CEP*CET*PE TC = Q0*Q1*Q2*Q3*CET
Rev.2.00, Jul.16.2004, page 2 of 8
HD74ACT161/HD74ACT163
Mode Select Table
SR*1 SR L H H H H Note: X L H H H PE X X H L X CET X X H X L CEP Action on the Rising Clock Edge ( Reset (Clear) Load (Pn Qn) Count (Increment) No change (Hold) No change (Hold) )
1. For HD74ACT163 H : High Voltage Level L : Low Voltage Level X : Immaterial
State Diagram
0 1 2 3 4
15
5
14
6
13
7
12
11
10
9
8
Block Diagram
P0 PE '161 '163 CEP CET '163 ONRY P1 P2 P3
TC
CP
CP
'161 ONRY
CP D CP D CD Q Q
Q0
Q0 DETAIL A
DETAIL A
DETAIL A
DETAIL A
MR '161 SR '163 Q0 Q1 Q2 Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Rev.2.00, Jul.16.2004, page 3 of 8
HD74ACT161/HD74ACT163
Absolute Maximum Ratings
Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C Condition VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V
Recommended Operating Conditions
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 4.5V VCC = 5.5V Unit Condition
DC Characteristics
Item Symbol VIH VIL Output voltage VOH VCC (V) min. Input voltage 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL 4.5 5.5 4.5 5.5 Input current ICC/input current Dynamic output current* Quiescent supply current IIN ICCT IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 2.0 2.0 -- -- 4.4 5.4 3.94 4.94 -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 1.5 1.5 1.5 4.49 5.49 -- -- 0.001 0.001 -- -- -- 0.6 -- -- -- max. -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.32 0.32 0.1 -- -- -- 8.0 Ta = -40 to +85C min. max. 2.0 2.0 -- -- 4.4 5.4 3.80 4.80 -- -- -- -- -- -- 86 -75 -- -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.37 0.37 1.0 1.5 -- -- 80 A mA mA mA A V Unit Condition
V
VOUT = 0.1 V or Vcc-0.1 V VOUT = 0.1 V or Vcc-0.1 V VIN = VIL or VIH IOUT = -50 A VIN = VIL VIN = VIL or VIH IOUT = 50 A VIN = VIL VIN = VCC or GND VIN = VCC-2.1 V VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground IOL = 24 mA IOL = 24 mA IOH = -24 mA IOH = -24 mA
*Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 4 of 8
HD74ACT161/HD74ACT163
AC Characteristics: HD74ACT161
Ta = +25C CL = 50 pF Item Maximum count frequency Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to TC Propagation delay CP to TC Propagation delay CET to TC Propagation delay CET to TC Propagation delay MR to Qn Propagation delay MR to TC Note: Symbol fmax tPLH VCC (V)*1 Min 5.0 115 5.0 1.0 Typ 125 5.5 Max -- 9.5 Ta = -40C to +85C CL = 50 pF Min 100 1.0 -- 10.5 Max MHz ns Unit
tPLH
5.0
1.0
6.0
10.5
1.0
11.5
ns
tPLH tPHL tPLH tPHL tPHL tPHL
5.0 5.0 5.0 5.0 5.0 5.0
1.0 1.0 1.0 1.0 1.0 1.0
7.0 8.0 5.5 6.0 6.0 8.0
11.0 12.5 8.5 9.5 10.0 13.5
1.0 1.0 1.0 1.0 1.0 1.0
12.5 13.5 10.0 10.5 11.0 14.5
ns ns ns ns ns ns
1. Voltage Range 5.0 is 5.0 V 0.5 V
AC Operating Requirements: HD74ACT161
Ta = +25C CL = 50 pF Item Set-up time, HIGH or LOW Pn to CP Hold time, HIGH or LOW Pn to CP Setup time, HIGH or LOW MR to CP Hold time, HIGH or LOW MR to CP Setup time, HIGH or LOW PE to CP Hold time, HIGH or LOW PE to CP Setup time, HIGH or LOW CEP or CET to CP Hold time, HIGH or LOW CEP or CET to CP Clock pulse width (Load) HIGH or LOW Clock pulse width (Count) HIGH or LOW MR pulse width, LOW Recovery time MR to CP Note: Symbol VCC (V)*1 Typ 5.0 4.0 tsu th tsu th tsu th tsu th tw tw tw trec 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 -5.0 4.0 -5.5 4.0 -5.5 2.5 -3.0 2.0 2.0 3.0 0 Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns ns ns ns ns ns ns ns ns
Guaranteed Minimum 9.5 11.5 0 8.5 -0.5 8.5 -0.5 5.5 0 3.0 3.0 3.0 0 0 9.5 -0.5 9.5 -0.5 6.5 0 3.5 3.5 7.5 0.5
1. Voltage Range 5.0 is 5.0 V 0.5 V
Rev.2.00, Jul.16.2004, page 5 of 8
HD74ACT161/HD74ACT163
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 45.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
AC Characteristics: HD74ACT163
Ta = +25C CL = 50 pF Item Maximum count frequency Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to Qn (PE Input HIGH or LOW) Propagation delay CP to TC Propagation delay CP to TC Propagation delay CET to TC Propagation delay CET to TC Note: Symbol fmax tPLH VCC (V)*1 Min 5.0 120 5.0 1.0 Typ 128 5.5 Max -- 10.0 Ta = -40C to +85C CL = 50 pF Min 105 1.0 -- 11.0 Max MHz ns Unit
tPHL
5.0
1.0
6.0
11.0
1.0
12.0
ns
tPLH tPHL tPLH tPHL
5.0 5.0 5.0 5.0
1.0 1.0 1.0 1.0
7.0 8.0 5.5 6.0
11.5 13.5 9.0 10.0
1.0 1.0 1.0 1.0
13.5 15.0 10.5 11.0
ns ns ns ns
1. Voltage Range 5.0 is 5.0 V 0.5 V
AC Operating Requirements: HD74ACT163
Ta = +25C CL = 50 pF Item Symbol VCC (V)*1 Set-up time, HIGH or LOW 5.0 tsu Pn to CP Hold time, HIGH or LOW 5.0 th Pn to CP Setup time, HIGH or LOW 5.0 tsu SR to CP Hold time, HIGH or LOW 5.0 th SR to CP Setup time, HIGH or LOW 5.0 tsu PE to CP Hold time, HIGH or LOW 5.0 th PE to CP Setup time, HIGH or LOW tsu 5.0 CEP or CET to CP Hold time, HIGH or LOW 5.0 th CEP or CET to CP Clock pulse width (Load) tw 5.0 HIGH or LOW Clock pulse width (Count) 5.0 tw HIGH or LOW Note: 1. Voltage Range 5.0 is 5.0 V 0.5 V Typ 4.0 -5.0 4.0 -5.5 4.0 -5.5 2.5 -3.0 2.0 2.0 Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns ns ns ns ns ns ns
Guaranteed Minimum 10.0 12.0 0.5 10.0 -0.5 8.5 -0.5 5.5 0 3.5 3.5 0.5 11.5 -0.5 10.5 0 6.5 0.5 3.5 3.5
Rev.2.00, Jul.16.2004, page 6 of 8
HD74ACT161/HD74ACT163
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 45.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
Rev.2.00, Jul.16.2004, page 7 of 8
HD74ACT161/HD74ACT163
Package Dimensions
As of January, 2003
10.06 10.5 Max 16 9
5.5
Unit: mm
1
*0.20 0.05
8
0.80 Max
2.20 Max
0.20 7.80 + 0.30 -
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9 10.3 Max 16 9
3.95
1 1.27 0.635 Max
8
0.11 0.14 + 0.04 - 1.75 Max
*0.20 0.05
0.10 6.10 + 0.30 -
1.08
0 - 8
+ 0.67 0.60 - 0.20
*0.40 0.06
0.15 0.25 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-16DNV Conforms Conforms 0.15 g
Rev.2.00, Jul.16.2004, page 8 of 8
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